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<div class="title">xaxipcie_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gab5e38a3a5815c463c52461a8f7f52b75"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gab5e38a3a5815c463c52461a8f7f52b75">XAxiPcie_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:gab5e38a3a5815c463c52461a8f7f52b75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to read register.  <a href="group__axipcie.html#gab5e38a3a5815c463c52461a8f7f52b75">More...</a><br/></td></tr>
<tr class="separator:gab5e38a3a5815c463c52461a8f7f52b75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3312e39c24adeb6a06a7408a68a1e80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaf3312e39c24adeb6a06a7408a68a1e80">XAxiPcie_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:gaf3312e39c24adeb6a06a7408a68a1e80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to write register.  <a href="group__axipcie.html#gaf3312e39c24adeb6a06a7408a68a1e80">More...</a><br/></td></tr>
<tr class="separator:gaf3312e39c24adeb6a06a7408a68a1e80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for this device.</p>
<p>Some of the registers are configurable at hardware build time such that may or may not exist in the hardware. </p>
</div></td></tr>
<tr class="memitem:ga7cecef23e8a28935226e7dc9815390c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga7cecef23e8a28935226e7dc9815390c0">XAXIPCIE_PCIE_CORE_OFFSET</a>&#160;&#160;&#160;0x000</td></tr>
<tr class="memdesc:ga7cecef23e8a28935226e7dc9815390c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCI Express hard core configuration register offset.  <a href="group__axipcie.html#ga7cecef23e8a28935226e7dc9815390c0">More...</a><br/></td></tr>
<tr class="separator:ga7cecef23e8a28935226e7dc9815390c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf01ed785ab64d6c124437532ece335ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaf01ed785ab64d6c124437532ece335ce">XAXIPCIE_VSECC_OFFSET</a>&#160;&#160;&#160;0x128</td></tr>
<tr class="memdesc:gaf01ed785ab64d6c124437532ece335ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">VSEC Capability Register.  <a href="group__axipcie.html#gaf01ed785ab64d6c124437532ece335ce">More...</a><br/></td></tr>
<tr class="separator:gaf01ed785ab64d6c124437532ece335ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab99ecd675b55df50a385fc7b429d38e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gab99ecd675b55df50a385fc7b429d38e4">XAXIPCIE_VSECH_OFFSET</a>&#160;&#160;&#160;0x12C</td></tr>
<tr class="memdesc:gab99ecd675b55df50a385fc7b429d38e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">VSEC Header Register.  <a href="group__axipcie.html#gab99ecd675b55df50a385fc7b429d38e4">More...</a><br/></td></tr>
<tr class="separator:gab99ecd675b55df50a385fc7b429d38e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f8bb352119692caff9e7851fe534498"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga9f8bb352119692caff9e7851fe534498">XAXIPCIE_BI_OFFSET</a>&#160;&#160;&#160;0x130</td></tr>
<tr class="memdesc:ga9f8bb352119692caff9e7851fe534498"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Info Register.  <a href="group__axipcie.html#ga9f8bb352119692caff9e7851fe534498">More...</a><br/></td></tr>
<tr class="separator:ga9f8bb352119692caff9e7851fe534498"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10e385edef3931106642fcf07d5a5fec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga10e385edef3931106642fcf07d5a5fec">XAXIPCIE_BSC_OFFSET</a>&#160;&#160;&#160;0x134</td></tr>
<tr class="memdesc:ga10e385edef3931106642fcf07d5a5fec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Status and Control Register.  <a href="group__axipcie.html#ga10e385edef3931106642fcf07d5a5fec">More...</a><br/></td></tr>
<tr class="separator:ga10e385edef3931106642fcf07d5a5fec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4ee25f8cd866c3c4c79bd9f1a784a7c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaf4ee25f8cd866c3c4c79bd9f1a784a7c">XAXIPCIE_ID_OFFSET</a>&#160;&#160;&#160;0x138</td></tr>
<tr class="memdesc:gaf4ee25f8cd866c3c4c79bd9f1a784a7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Decode Register.  <a href="group__axipcie.html#gaf4ee25f8cd866c3c4c79bd9f1a784a7c">More...</a><br/></td></tr>
<tr class="separator:gaf4ee25f8cd866c3c4c79bd9f1a784a7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad798e4bbf2fc4fe5135dfa56fac31399"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gad798e4bbf2fc4fe5135dfa56fac31399">XAXIPCIE_IM_OFFSET</a>&#160;&#160;&#160;0x13C</td></tr>
<tr class="memdesc:gad798e4bbf2fc4fe5135dfa56fac31399"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Mask Register.  <a href="group__axipcie.html#gad798e4bbf2fc4fe5135dfa56fac31399">More...</a><br/></td></tr>
<tr class="separator:gad798e4bbf2fc4fe5135dfa56fac31399"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8a758a6bb3b73be59a403a53ef97881"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gae8a758a6bb3b73be59a403a53ef97881">XAXIPCIE_BL_OFFSET</a>&#160;&#160;&#160;0x140</td></tr>
<tr class="memdesc:gae8a758a6bb3b73be59a403a53ef97881"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Location Register.  <a href="group__axipcie.html#gae8a758a6bb3b73be59a403a53ef97881">More...</a><br/></td></tr>
<tr class="separator:gae8a758a6bb3b73be59a403a53ef97881"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84f89f155288e2a5de41a09bdf5d8672"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga84f89f155288e2a5de41a09bdf5d8672">XAXIPCIE_PHYSC_OFFSET</a>&#160;&#160;&#160;0x144</td></tr>
<tr class="memdesc:ga84f89f155288e2a5de41a09bdf5d8672"><td class="mdescLeft">&#160;</td><td class="mdescRight">Physical status and Control Register.  <a href="group__axipcie.html#ga84f89f155288e2a5de41a09bdf5d8672">More...</a><br/></td></tr>
<tr class="separator:ga84f89f155288e2a5de41a09bdf5d8672"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb8cd2a16037d697cf4a5af55506af44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gafb8cd2a16037d697cf4a5af55506af44">XAXIPCIE_RPSC_OFFSET</a>&#160;&#160;&#160;0x148</td></tr>
<tr class="memdesc:gafb8cd2a16037d697cf4a5af55506af44"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Status &amp; Control Register.  <a href="group__axipcie.html#gafb8cd2a16037d697cf4a5af55506af44">More...</a><br/></td></tr>
<tr class="separator:gafb8cd2a16037d697cf4a5af55506af44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b498715d2bbafc1a81fea7abd853f29"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga5b498715d2bbafc1a81fea7abd853f29">XAXIPCIE_RPMSIB_UPPER_OFFSET</a>&#160;&#160;&#160;0x14C</td></tr>
<tr class="memdesc:ga5b498715d2bbafc1a81fea7abd853f29"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port MSI Base 1 Register Upper 32 bits from 64 bit address are written.  <a href="group__axipcie.html#ga5b498715d2bbafc1a81fea7abd853f29">More...</a><br/></td></tr>
<tr class="separator:ga5b498715d2bbafc1a81fea7abd853f29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fff8ece26635ba08deb9dd05f6283a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga7fff8ece26635ba08deb9dd05f6283a1">XAXIPCIE_RPMSIB_LOWER_OFFSET</a>&#160;&#160;&#160;0x150</td></tr>
<tr class="memdesc:ga7fff8ece26635ba08deb9dd05f6283a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port MSI Base 2 Register Lower 32 bits from 64 bit address are written.  <a href="group__axipcie.html#ga7fff8ece26635ba08deb9dd05f6283a1">More...</a><br/></td></tr>
<tr class="separator:ga7fff8ece26635ba08deb9dd05f6283a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e3c116efe4ad6fc7c0d87a4fdea9dab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga8e3c116efe4ad6fc7c0d87a4fdea9dab">XAXIPCIE_RPEFR_OFFSET</a>&#160;&#160;&#160;0x154</td></tr>
<tr class="memdesc:ga8e3c116efe4ad6fc7c0d87a4fdea9dab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Read Register.  <a href="group__axipcie.html#ga8e3c116efe4ad6fc7c0d87a4fdea9dab">More...</a><br/></td></tr>
<tr class="separator:ga8e3c116efe4ad6fc7c0d87a4fdea9dab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad61ae31bb34ed3e02243c5d74ac75afa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gad61ae31bb34ed3e02243c5d74ac75afa">XAXIPCIE_RPIFR1_OFFSET</a>&#160;&#160;&#160;0x158</td></tr>
<tr class="memdesc:gad61ae31bb34ed3e02243c5d74ac75afa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Read1 Register.  <a href="group__axipcie.html#gad61ae31bb34ed3e02243c5d74ac75afa">More...</a><br/></td></tr>
<tr class="separator:gad61ae31bb34ed3e02243c5d74ac75afa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga92a83142f665f34045a5235732060c47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga92a83142f665f34045a5235732060c47">XAXIPCIE_RPIFR2_OFFSET</a>&#160;&#160;&#160;0x15C</td></tr>
<tr class="memdesc:ga92a83142f665f34045a5235732060c47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Read2 Register.  <a href="group__axipcie.html#ga92a83142f665f34045a5235732060c47">More...</a><br/></td></tr>
<tr class="separator:ga92a83142f665f34045a5235732060c47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace702755df9d438185fdb96c5e63cc0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gace702755df9d438185fdb96c5e63cc0e">XAXIPCIE_AXIBAR2PCIBAR_0U_OFFSET</a>&#160;&#160;&#160;0x208</td></tr>
<tr class="memdesc:gace702755df9d438185fdb96c5e63cc0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR 2 PCIBAR translation 0 upper 32 bits.  <a href="group__axipcie.html#gace702755df9d438185fdb96c5e63cc0e">More...</a><br/></td></tr>
<tr class="separator:gace702755df9d438185fdb96c5e63cc0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa01b566fdaa57bf0696c4a4445053158"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaa01b566fdaa57bf0696c4a4445053158">XAXIPCIE_AXIBAR2PCIBAR_0L_OFFSET</a>&#160;&#160;&#160;0x20C</td></tr>
<tr class="memdesc:gaa01b566fdaa57bf0696c4a4445053158"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 0 lower 32 bits.  <a href="group__axipcie.html#gaa01b566fdaa57bf0696c4a4445053158">More...</a><br/></td></tr>
<tr class="separator:gaa01b566fdaa57bf0696c4a4445053158"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf2f3ccb2ad35296c9ad8fbd7658cfc9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gadf2f3ccb2ad35296c9ad8fbd7658cfc9">XAXIPCIE_AXIBAR2PCIBAR_1U_OFFSET</a>&#160;&#160;&#160;0x210</td></tr>
<tr class="memdesc:gadf2f3ccb2ad35296c9ad8fbd7658cfc9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 1 upper 32 bits.  <a href="group__axipcie.html#gadf2f3ccb2ad35296c9ad8fbd7658cfc9">More...</a><br/></td></tr>
<tr class="separator:gadf2f3ccb2ad35296c9ad8fbd7658cfc9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6abf854a95cdb33425df188de3e63491"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga6abf854a95cdb33425df188de3e63491">XAXIPCIE_AXIBAR2PCIBAR_1L_OFFSET</a>&#160;&#160;&#160;0x214</td></tr>
<tr class="memdesc:ga6abf854a95cdb33425df188de3e63491"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 1 lower 32 bits.  <a href="group__axipcie.html#ga6abf854a95cdb33425df188de3e63491">More...</a><br/></td></tr>
<tr class="separator:ga6abf854a95cdb33425df188de3e63491"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac6b872ead955b2775dfd68c8cdaece4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gac6b872ead955b2775dfd68c8cdaece4b">XAXIPCIE_AXIBAR2PCIBAR_2U_OFFSET</a>&#160;&#160;&#160;0x218</td></tr>
<tr class="memdesc:gac6b872ead955b2775dfd68c8cdaece4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 2 upper 32 bits.  <a href="group__axipcie.html#gac6b872ead955b2775dfd68c8cdaece4b">More...</a><br/></td></tr>
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<tr class="memitem:ga60190c47d9ac660c226563032207ebb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga60190c47d9ac660c226563032207ebb3">XAXIPCIE_AXIBAR2PCIBAR_2L_OFFSET</a>&#160;&#160;&#160;0x21C</td></tr>
<tr class="memdesc:ga60190c47d9ac660c226563032207ebb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 2 lower 32 bits.  <a href="group__axipcie.html#ga60190c47d9ac660c226563032207ebb3">More...</a><br/></td></tr>
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<tr class="memitem:ga165a875ba9d89b26ebb25cb288c33745"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga165a875ba9d89b26ebb25cb288c33745">XAXIPCIE_AXIBAR2PCIBAR_3L_OFFSET</a>&#160;&#160;&#160;0x224</td></tr>
<tr class="memdesc:ga165a875ba9d89b26ebb25cb288c33745"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 3 lower 32 bits.  <a href="group__axipcie.html#ga165a875ba9d89b26ebb25cb288c33745">More...</a><br/></td></tr>
<tr class="separator:ga165a875ba9d89b26ebb25cb288c33745"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7970a09db54b7f198a039211a1116b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaa7970a09db54b7f198a039211a1116b3">XAXIPCIE_AXIBAR2PCIBAR_4U_OFFSET</a>&#160;&#160;&#160;0x228</td></tr>
<tr class="memdesc:gaa7970a09db54b7f198a039211a1116b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 4 upper 32 bits.  <a href="group__axipcie.html#gaa7970a09db54b7f198a039211a1116b3">More...</a><br/></td></tr>
<tr class="separator:gaa7970a09db54b7f198a039211a1116b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga940f71ca9d3e3bc7ac6716f2f34c4884"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga940f71ca9d3e3bc7ac6716f2f34c4884">XAXIPCIE_AXIBAR2PCIBAR_4L_OFFSET</a>&#160;&#160;&#160;0x22C</td></tr>
<tr class="memdesc:ga940f71ca9d3e3bc7ac6716f2f34c4884"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 4 lower 32 bits.  <a href="group__axipcie.html#ga940f71ca9d3e3bc7ac6716f2f34c4884">More...</a><br/></td></tr>
<tr class="separator:ga940f71ca9d3e3bc7ac6716f2f34c4884"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe4237b20c412dc42cbd47c8bd87af92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gabe4237b20c412dc42cbd47c8bd87af92">XAXIPCIE_AXIBAR2PCIBAR_5U_OFFSET</a>&#160;&#160;&#160;0x230</td></tr>
<tr class="memdesc:gabe4237b20c412dc42cbd47c8bd87af92"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 5 upper 32 bits.  <a href="group__axipcie.html#gabe4237b20c412dc42cbd47c8bd87af92">More...</a><br/></td></tr>
<tr class="separator:gabe4237b20c412dc42cbd47c8bd87af92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga400d8b2257870a70418b3d9bf8de5a77"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga400d8b2257870a70418b3d9bf8de5a77">XAXIPCIE_AXIBAR2PCIBAR_5L_OFFSET</a>&#160;&#160;&#160;0x234</td></tr>
<tr class="memdesc:ga400d8b2257870a70418b3d9bf8de5a77"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 5 lower 32 bits.  <a href="group__axipcie.html#ga400d8b2257870a70418b3d9bf8de5a77">More...</a><br/></td></tr>
<tr class="separator:ga400d8b2257870a70418b3d9bf8de5a77"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">VSECC Register bitmaps and masks</div></td></tr>
<tr class="memitem:gabd84445ebce4bfcb25ca5b75799bbba5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gabd84445ebce4bfcb25ca5b75799bbba5">XAXIPCIE_VSECC_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gabd84445ebce4bfcb25ca5b75799bbba5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec capability Id.  <a href="group__axipcie.html#gabd84445ebce4bfcb25ca5b75799bbba5">More...</a><br/></td></tr>
<tr class="separator:gabd84445ebce4bfcb25ca5b75799bbba5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8724baa412ffd4bd593fd67c2928c3a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga8724baa412ffd4bd593fd67c2928c3a1">XAXIPCIE_VSECC_VER_MASK</a>&#160;&#160;&#160;0x000F0000</td></tr>
<tr class="memdesc:ga8724baa412ffd4bd593fd67c2928c3a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version of capability Structure.  <a href="group__axipcie.html#ga8724baa412ffd4bd593fd67c2928c3a1">More...</a><br/></td></tr>
<tr class="separator:ga8724baa412ffd4bd593fd67c2928c3a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca2f85036ff847a8f3c9def6d402bfe3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaca2f85036ff847a8f3c9def6d402bfe3">XAXIPCIE_VSECC_NEXT_MASK</a>&#160;&#160;&#160;0xFFF00000</td></tr>
<tr class="memdesc:gaca2f85036ff847a8f3c9def6d402bfe3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset to next capability.  <a href="group__axipcie.html#gaca2f85036ff847a8f3c9def6d402bfe3">More...</a><br/></td></tr>
<tr class="separator:gaca2f85036ff847a8f3c9def6d402bfe3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab791a04d374dfc7d88d5e3c817126b8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gab791a04d374dfc7d88d5e3c817126b8f">XAXIPCIE_VSECC_VER_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gab791a04d374dfc7d88d5e3c817126b8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">VSEC Version shift.  <a href="group__axipcie.html#gab791a04d374dfc7d88d5e3c817126b8f">More...</a><br/></td></tr>
<tr class="separator:gab791a04d374dfc7d88d5e3c817126b8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4ea49e123b5a60e753034437e748a455"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga4ea49e123b5a60e753034437e748a455">XAXIPCIE_VSECC_NEXT_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:ga4ea49e123b5a60e753034437e748a455"><td class="mdescLeft">&#160;</td><td class="mdescRight">Next capability offset shift.  <a href="group__axipcie.html#ga4ea49e123b5a60e753034437e748a455">More...</a><br/></td></tr>
<tr class="separator:ga4ea49e123b5a60e753034437e748a455"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">VSECH Register bitmaps and masks</div></td></tr>
<tr class="memitem:gafd846b29aae82d036fc3ea66ef65596f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gafd846b29aae82d036fc3ea66ef65596f">XAXIPCIE_VSECH_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gafd846b29aae82d036fc3ea66ef65596f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec structure Id.  <a href="group__axipcie.html#gafd846b29aae82d036fc3ea66ef65596f">More...</a><br/></td></tr>
<tr class="separator:gafd846b29aae82d036fc3ea66ef65596f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94c0af68259b5949d6c003dd85d46b2d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga94c0af68259b5949d6c003dd85d46b2d">XAXIPCIE_VSECH_REV_MASK</a>&#160;&#160;&#160;0x000F0000</td></tr>
<tr class="memdesc:ga94c0af68259b5949d6c003dd85d46b2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec header version.  <a href="group__axipcie.html#ga94c0af68259b5949d6c003dd85d46b2d">More...</a><br/></td></tr>
<tr class="separator:ga94c0af68259b5949d6c003dd85d46b2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed6b0e6cd2817f7c5c69c3290833447e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaed6b0e6cd2817f7c5c69c3290833447e">XAXIPCIE_VSECH_LEN_MASK</a>&#160;&#160;&#160;0xFFF00000</td></tr>
<tr class="memdesc:gaed6b0e6cd2817f7c5c69c3290833447e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Length of Vsec capability structure.  <a href="group__axipcie.html#gaed6b0e6cd2817f7c5c69c3290833447e">More...</a><br/></td></tr>
<tr class="separator:gaed6b0e6cd2817f7c5c69c3290833447e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga591f34e1c213bb45aba99629c71b565b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga591f34e1c213bb45aba99629c71b565b">XAXIPCIE_VSECH_REV_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga591f34e1c213bb45aba99629c71b565b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec version shift.  <a href="group__axipcie.html#ga591f34e1c213bb45aba99629c71b565b">More...</a><br/></td></tr>
<tr class="separator:ga591f34e1c213bb45aba99629c71b565b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa6e2e6e5e712fa8b44077688caee37d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaa6e2e6e5e712fa8b44077688caee37d1">XAXIPCIE_VSECH_LEN_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:gaa6e2e6e5e712fa8b44077688caee37d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec length shift.  <a href="group__axipcie.html#gaa6e2e6e5e712fa8b44077688caee37d1">More...</a><br/></td></tr>
<tr class="separator:gaa6e2e6e5e712fa8b44077688caee37d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bridge Info Register bitmaps and masks</div></td></tr>
<tr class="memitem:ga5c3e13956927d814f89b16d58bc87b71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga5c3e13956927d814f89b16d58bc87b71">XAXIPCIE_BI_GEN2_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga5c3e13956927d814f89b16d58bc87b71"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Gen2 Speed Support Mask.  <a href="group__axipcie.html#ga5c3e13956927d814f89b16d58bc87b71">More...</a><br/></td></tr>
<tr class="separator:ga5c3e13956927d814f89b16d58bc87b71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab624cf074fe8d343c15a086782e1150c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gab624cf074fe8d343c15a086782e1150c">XAXIPCIE_BI_RP_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gab624cf074fe8d343c15a086782e1150c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Root Port Support.  <a href="group__axipcie.html#gab624cf074fe8d343c15a086782e1150c">More...</a><br/></td></tr>
<tr class="separator:gab624cf074fe8d343c15a086782e1150c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3950d5b04a69dcbc2e2c5711cb657745"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga3950d5b04a69dcbc2e2c5711cb657745">XAXIPCIE_UP_CONFIG_CAPABLE</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga3950d5b04a69dcbc2e2c5711cb657745"><td class="mdescLeft">&#160;</td><td class="mdescRight">Up Config Capable.  <a href="group__axipcie.html#ga3950d5b04a69dcbc2e2c5711cb657745">More...</a><br/></td></tr>
<tr class="separator:ga3950d5b04a69dcbc2e2c5711cb657745"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d99e62d5248da57465cd526eaf9cb01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga2d99e62d5248da57465cd526eaf9cb01">XAXIPCIE_BI_ECAM_SIZE_MASK</a>&#160;&#160;&#160;0x00070000</td></tr>
<tr class="memdesc:ga2d99e62d5248da57465cd526eaf9cb01"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECAM size.  <a href="group__axipcie.html#ga2d99e62d5248da57465cd526eaf9cb01">More...</a><br/></td></tr>
<tr class="separator:ga2d99e62d5248da57465cd526eaf9cb01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae20709cf0062b87ed8689af2e8ee0a0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gae20709cf0062b87ed8689af2e8ee0a0a">XAXIPCIE_BI_RP_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gae20709cf0062b87ed8689af2e8ee0a0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Root Port Shift.  <a href="group__axipcie.html#gae20709cf0062b87ed8689af2e8ee0a0a">More...</a><br/></td></tr>
<tr class="separator:gae20709cf0062b87ed8689af2e8ee0a0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e5ee78d2b39fa90a87fea37ed49d35a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga6e5ee78d2b39fa90a87fea37ed49d35a">XAXIPCIE_BI_ECAM_SIZE_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga6e5ee78d2b39fa90a87fea37ed49d35a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe ECAM Size Shift.  <a href="group__axipcie.html#ga6e5ee78d2b39fa90a87fea37ed49d35a">More...</a><br/></td></tr>
<tr class="separator:ga6e5ee78d2b39fa90a87fea37ed49d35a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bridge Status &amp; Control Register bitmaps and masks</div></td></tr>
<tr class="memitem:gabfb6e478c3f181fcec8e4918f9442296"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gabfb6e478c3f181fcec8e4918f9442296">XAXIPCIE_BSC_ECAM_BUSY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gabfb6e478c3f181fcec8e4918f9442296"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECAM Busy Status.  <a href="group__axipcie.html#gabfb6e478c3f181fcec8e4918f9442296">More...</a><br/></td></tr>
<tr class="separator:gabfb6e478c3f181fcec8e4918f9442296"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a80436f1d395be5d4963d3f9d09f49c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga6a80436f1d395be5d4963d3f9d09f49c">XAXIPCIE_BSC_GI_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga6a80436f1d395be5d4963d3f9d09f49c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Disable.  <a href="group__axipcie.html#ga6a80436f1d395be5d4963d3f9d09f49c">More...</a><br/></td></tr>
<tr class="separator:ga6a80436f1d395be5d4963d3f9d09f49c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d8d34b56c828dc51ee2bf7fe5876e6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga5d8d34b56c828dc51ee2bf7fe5876e6d">XAXIPCIE_BSC_RW1C_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:ga5d8d34b56c828dc51ee2bf7fe5876e6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">RW Permissions to RW1C Registers.  <a href="group__axipcie.html#ga5d8d34b56c828dc51ee2bf7fe5876e6d">More...</a><br/></td></tr>
<tr class="separator:ga5d8d34b56c828dc51ee2bf7fe5876e6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7414766d143e8d20bf6ace5ca03548d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga7414766d143e8d20bf6ace5ca03548d8">XAXIPCIE_BSC_RO_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:ga7414766d143e8d20bf6ace5ca03548d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">RW Permissions to RO Registers.  <a href="group__axipcie.html#ga7414766d143e8d20bf6ace5ca03548d8">More...</a><br/></td></tr>
<tr class="separator:ga7414766d143e8d20bf6ace5ca03548d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga92e6aa96f3a966ac3ac8b8b00bb770e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga92e6aa96f3a966ac3ac8b8b00bb770e6">XAXIPCIE_BSC_GI_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga92e6aa96f3a966ac3ac8b8b00bb770e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Disable Shift.  <a href="group__axipcie.html#ga92e6aa96f3a966ac3ac8b8b00bb770e6">More...</a><br/></td></tr>
<tr class="separator:ga92e6aa96f3a966ac3ac8b8b00bb770e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac17ec341d56663eee8c61f478078e8e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gac17ec341d56663eee8c61f478078e8e5">XAXIPCIE_BSC_RW1C_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gac17ec341d56663eee8c61f478078e8e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">RW1C Shift.  <a href="group__axipcie.html#gac17ec341d56663eee8c61f478078e8e5">More...</a><br/></td></tr>
<tr class="separator:gac17ec341d56663eee8c61f478078e8e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00ae2b626af9f11c9e3f9ccf4cbbd526"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga00ae2b626af9f11c9e3f9ccf4cbbd526">XAXIPCIE_BSC_RO_SHIFT</a>&#160;&#160;&#160;17</td></tr>
<tr class="memdesc:ga00ae2b626af9f11c9e3f9ccf4cbbd526"><td class="mdescLeft">&#160;</td><td class="mdescRight">RO as RW Shift.  <a href="group__axipcie.html#ga00ae2b626af9f11c9e3f9ccf4cbbd526">More...</a><br/></td></tr>
<tr class="separator:ga00ae2b626af9f11c9e3f9ccf4cbbd526"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Decode Register bitmaps and masks</div></td></tr>
<tr class="memitem:ga7d8d223d3881fc8e39d0d176974a5f97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga7d8d223d3881fc8e39d0d176974a5f97">XAXIPCIE_ID_LINK_DOWN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga7d8d223d3881fc8e39d0d176974a5f97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Down Mask.  <a href="group__axipcie.html#ga7d8d223d3881fc8e39d0d176974a5f97">More...</a><br/></td></tr>
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<tr class="memitem:gac24578f59c89ad7e659b6321259e005c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gac24578f59c89ad7e659b6321259e005c">XAXIPCIE_ID_ECRC_ERR_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gac24578f59c89ad7e659b6321259e005c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Packet CRC failed.  <a href="group__axipcie.html#gac24578f59c89ad7e659b6321259e005c">More...</a><br/></td></tr>
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<tr class="memitem:gac12ef40af613a60dd229b11010e850ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gac12ef40af613a60dd229b11010e850ef">XAXIPCIE_ID_STR_ERR_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gac12ef40af613a60dd229b11010e850ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Error Mask.  <a href="group__axipcie.html#gac12ef40af613a60dd229b11010e850ef">More...</a><br/></td></tr>
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<tr class="memitem:gab7c127293e67e001584800088d052fee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gab7c127293e67e001584800088d052fee">XAXIPCIE_ID_HOT_RST_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gab7c127293e67e001584800088d052fee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hot Reset Mask.  <a href="group__axipcie.html#gab7c127293e67e001584800088d052fee">More...</a><br/></td></tr>
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<tr class="memitem:ga846f47d9802bd878b3903c27673e4242"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga846f47d9802bd878b3903c27673e4242">XAXIPCIE_ID_CFG_COMPL_STATE_MASK</a>&#160;&#160;&#160;0x000000E0</td></tr>
<tr class="memdesc:ga846f47d9802bd878b3903c27673e4242"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cfg Completion Status Mask.  <a href="group__axipcie.html#ga846f47d9802bd878b3903c27673e4242">More...</a><br/></td></tr>
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<tr class="memitem:ga5d2598bc52c54ea03294b1ddd915611a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga5d2598bc52c54ea03294b1ddd915611a">XAXIPCIE_ID_CFG_TIMEOUT_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga5d2598bc52c54ea03294b1ddd915611a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cfg timeout Mask.  <a href="group__axipcie.html#ga5d2598bc52c54ea03294b1ddd915611a">More...</a><br/></td></tr>
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<tr class="memitem:ga96cd9b31642245e067b4f746cd38a238"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga96cd9b31642245e067b4f746cd38a238">XAXIPCIE_ID_CORRECTABLE_ERR_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga96cd9b31642245e067b4f746cd38a238"><td class="mdescLeft">&#160;</td><td class="mdescRight">Correctable Error Mask.  <a href="group__axipcie.html#ga96cd9b31642245e067b4f746cd38a238">More...</a><br/></td></tr>
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<tr class="memitem:ga79e63cd543f66440b3b227807636ee90"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga79e63cd543f66440b3b227807636ee90">XAXIPCIE_ID_NONFATAL_ERR_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga79e63cd543f66440b3b227807636ee90"><td class="mdescLeft">&#160;</td><td class="mdescRight">Non-Fatal Error Mask.  <a href="group__axipcie.html#ga79e63cd543f66440b3b227807636ee90">More...</a><br/></td></tr>
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<tr class="memitem:ga193020c952d0d7ad38a3769887bd9d34"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga193020c952d0d7ad38a3769887bd9d34">XAXIPCIE_ID_FATAL_ERR_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga193020c952d0d7ad38a3769887bd9d34"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fatal Error Mask.  <a href="group__axipcie.html#ga193020c952d0d7ad38a3769887bd9d34">More...</a><br/></td></tr>
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<tr class="memitem:gacad1e038951dbef989a1d3b266af35c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gacad1e038951dbef989a1d3b266af35c9">XAXIPCIE_ID_INTX_INTERRUPT</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:gacad1e038951dbef989a1d3b266af35c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">INTX Interrupt.  <a href="group__axipcie.html#gacad1e038951dbef989a1d3b266af35c9">More...</a><br/></td></tr>
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<tr class="memitem:gaf6f510e8eb119a47dd7f0ebc16801fac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaf6f510e8eb119a47dd7f0ebc16801fac">XAXIPCIE_ID_MSI_INTERRUPT</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:gaf6f510e8eb119a47dd7f0ebc16801fac"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI Interrupt.  <a href="group__axipcie.html#gaf6f510e8eb119a47dd7f0ebc16801fac">More...</a><br/></td></tr>
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<tr class="memitem:gaa428513b46014681de2bf99c3cfac84e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaa428513b46014681de2bf99c3cfac84e">XAXIPCIE_ID_UNSUPP_CMPL_MASK</a>&#160;&#160;&#160;0x00100000</td></tr>
<tr class="memdesc:gaa428513b46014681de2bf99c3cfac84e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Unsupported Request Mask.  <a href="group__axipcie.html#gaa428513b46014681de2bf99c3cfac84e">More...</a><br/></td></tr>
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<tr class="memitem:ga16dc91d210fc5079a0c4aa475946818f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga16dc91d210fc5079a0c4aa475946818f">XAXIPCIE_ID_UNEXP_CMPL_MASK</a>&#160;&#160;&#160;0x00200000</td></tr>
<tr class="memdesc:ga16dc91d210fc5079a0c4aa475946818f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Unexpected Completion Mask.  <a href="group__axipcie.html#ga16dc91d210fc5079a0c4aa475946818f">More...</a><br/></td></tr>
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<tr class="memitem:gab0f88e6f4f242c99bd926d5db15cdb08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gab0f88e6f4f242c99bd926d5db15cdb08">XAXIPCIE_ID_CMPL_TIMEOUT_MASK</a>&#160;&#160;&#160;0x00400000</td></tr>
<tr class="memdesc:gab0f88e6f4f242c99bd926d5db15cdb08"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave completion Time Mask.  <a href="group__axipcie.html#gab0f88e6f4f242c99bd926d5db15cdb08">More...</a><br/></td></tr>
<tr class="separator:gab0f88e6f4f242c99bd926d5db15cdb08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1298f6ace7fb8944f15181c960a90beb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga1298f6ace7fb8944f15181c960a90beb">XAXIPCIE_ID_SLV_EP_MASK</a>&#160;&#160;&#160;0x00800000</td></tr>
<tr class="memdesc:ga1298f6ace7fb8944f15181c960a90beb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Error Poison Mask.  <a href="group__axipcie.html#ga1298f6ace7fb8944f15181c960a90beb">More...</a><br/></td></tr>
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<tr class="memitem:ga9d1319467ba4179502a8b4ef33bf4fe7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga9d1319467ba4179502a8b4ef33bf4fe7">XAXIPCIE_ID_CMPL_ABT_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:ga9d1319467ba4179502a8b4ef33bf4fe7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave completion Abort Mask.  <a href="group__axipcie.html#ga9d1319467ba4179502a8b4ef33bf4fe7">More...</a><br/></td></tr>
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<tr class="memitem:gae119f56dec65465b4438531840a8a759"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gae119f56dec65465b4438531840a8a759">XAXIPCIE_ID_ILL_BURST_MASK</a>&#160;&#160;&#160;0x02000000</td></tr>
<tr class="memdesc:gae119f56dec65465b4438531840a8a759"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Illegal Burst Mask.  <a href="group__axipcie.html#gae119f56dec65465b4438531840a8a759">More...</a><br/></td></tr>
<tr class="separator:gae119f56dec65465b4438531840a8a759"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c5b6ef607113d639e16d43dd05b9405"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga2c5b6ef607113d639e16d43dd05b9405">XAXIPCIE_ID_DECODE_ERR_MASK</a>&#160;&#160;&#160;0x04000000</td></tr>
<tr class="memdesc:ga2c5b6ef607113d639e16d43dd05b9405"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Decode Error Interrupt Mask.  <a href="group__axipcie.html#ga2c5b6ef607113d639e16d43dd05b9405">More...</a><br/></td></tr>
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<tr class="memitem:gaa6dd437acd81c0284bfd1ed1563cfbb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaa6dd437acd81c0284bfd1ed1563cfbb7">XAXIPCIE_ID_SLAVE_ERR_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:gaa6dd437acd81c0284bfd1ed1563cfbb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Slave Error Interrupt Mask.  <a href="group__axipcie.html#gaa6dd437acd81c0284bfd1ed1563cfbb7">More...</a><br/></td></tr>
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<tr class="memitem:ga96036ca77a405418f7e6da47d252f6c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga96036ca77a405418f7e6da47d252f6c9">XAXIPCIE_ID_MASTER_EP_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:ga96036ca77a405418f7e6da47d252f6c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Error Poison Mask.  <a href="group__axipcie.html#ga96036ca77a405418f7e6da47d252f6c9">More...</a><br/></td></tr>
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<tr class="memitem:gaeb7c330e5d10623ceafc66dd08f149ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaeb7c330e5d10623ceafc66dd08f149ea">XAXIPCIE_ID_CLEAR_ALL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gaeb7c330e5d10623ceafc66dd08f149ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of all Interrupts.  <a href="group__axipcie.html#gaeb7c330e5d10623ceafc66dd08f149ea">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt Mask Register bitmaps and masks</div></td></tr>
<tr class="memitem:ga40d5e3c669642af8441aed4d5ad23ee2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga40d5e3c669642af8441aed4d5ad23ee2">XAXIPCIE_IM_ENABLE_ALL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga40d5e3c669642af8441aed4d5ad23ee2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable All Interrupts.  <a href="group__axipcie.html#ga40d5e3c669642af8441aed4d5ad23ee2">More...</a><br/></td></tr>
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<tr class="memitem:ga1da6c8b6280b6726d8ac6178bf11af15"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga1da6c8b6280b6726d8ac6178bf11af15">XAXIPCIE_IM_DISABLE_ALL_MASK</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ga1da6c8b6280b6726d8ac6178bf11af15"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable All Interrupts.  <a href="group__axipcie.html#ga1da6c8b6280b6726d8ac6178bf11af15">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Bus Location Register bitmaps and masks</div></td></tr>
<tr class="memitem:ga269fecd1e2d8010e7b84e1339a5b2b94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga269fecd1e2d8010e7b84e1339a5b2b94">XAXIPCIE_BL_FUNC_MASK</a>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="memdesc:ga269fecd1e2d8010e7b84e1339a5b2b94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Function Number.  <a href="group__axipcie.html#ga269fecd1e2d8010e7b84e1339a5b2b94">More...</a><br/></td></tr>
<tr class="separator:ga269fecd1e2d8010e7b84e1339a5b2b94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21a35da125896346b1a3219fe2dfcc93"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga21a35da125896346b1a3219fe2dfcc93">XAXIPCIE_BL_DEV_MASK</a>&#160;&#160;&#160;0x000000F8</td></tr>
<tr class="memdesc:ga21a35da125896346b1a3219fe2dfcc93"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Device Number.  <a href="group__axipcie.html#ga21a35da125896346b1a3219fe2dfcc93">More...</a><br/></td></tr>
<tr class="separator:ga21a35da125896346b1a3219fe2dfcc93"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8a11f087363d5ff57409bf45a597851"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaf8a11f087363d5ff57409bf45a597851">XAXIPCIE_BL_BUS_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:gaf8a11f087363d5ff57409bf45a597851"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Bus Number.  <a href="group__axipcie.html#gaf8a11f087363d5ff57409bf45a597851">More...</a><br/></td></tr>
<tr class="separator:gaf8a11f087363d5ff57409bf45a597851"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae40bca0b490429edd0c59df2f04dd595"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gae40bca0b490429edd0c59df2f04dd595">XAXIPCIE_BL_PORT_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gae40bca0b490429edd0c59df2f04dd595"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Port Number.  <a href="group__axipcie.html#gae40bca0b490429edd0c59df2f04dd595">More...</a><br/></td></tr>
<tr class="separator:gae40bca0b490429edd0c59df2f04dd595"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0d3ce908be6f6c89a7212ddc42ba192"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaf0d3ce908be6f6c89a7212ddc42ba192">XAXIPCIE_BL_DEV_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gaf0d3ce908be6f6c89a7212ddc42ba192"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Device Number Shift Value.  <a href="group__axipcie.html#gaf0d3ce908be6f6c89a7212ddc42ba192">More...</a><br/></td></tr>
<tr class="separator:gaf0d3ce908be6f6c89a7212ddc42ba192"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc5afc68e0ece36131a9636a467ab327"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gadc5afc68e0ece36131a9636a467ab327">XAXIPCIE_BL_BUS_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gadc5afc68e0ece36131a9636a467ab327"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Bus Number Shift Value.  <a href="group__axipcie.html#gadc5afc68e0ece36131a9636a467ab327">More...</a><br/></td></tr>
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<tr class="memitem:ga7ef6bab98d1eba6156f808f92e39d7f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga7ef6bab98d1eba6156f808f92e39d7f2">XAXIPCIE_BL_PORT_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga7ef6bab98d1eba6156f808f92e39d7f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Bus Number Shift Value.  <a href="group__axipcie.html#ga7ef6bab98d1eba6156f808f92e39d7f2">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">PHY Status &amp; Control Register bitmaps and masks</div></td></tr>
<tr class="memitem:ga1238d2aba155c18a5ce7b45d2a1cbe39"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga1238d2aba155c18a5ce7b45d2a1cbe39">XAXIPCIE_PHYSC_LINK_RATE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga1238d2aba155c18a5ce7b45d2a1cbe39"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Rate.  <a href="group__axipcie.html#ga1238d2aba155c18a5ce7b45d2a1cbe39">More...</a><br/></td></tr>
<tr class="separator:ga1238d2aba155c18a5ce7b45d2a1cbe39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1afe809e17692a8fac45d860ac99c4d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga1afe809e17692a8fac45d860ac99c4d3">XAXIPCIE_PHYSC_LINK_WIDTH_MASK</a>&#160;&#160;&#160;0x00000006</td></tr>
<tr class="memdesc:ga1afe809e17692a8fac45d860ac99c4d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Width Mask.  <a href="group__axipcie.html#ga1afe809e17692a8fac45d860ac99c4d3">More...</a><br/></td></tr>
<tr class="separator:ga1afe809e17692a8fac45d860ac99c4d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga83dbe369846939579a0dd3d74476bcb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga83dbe369846939579a0dd3d74476bcb7">XAXIPCIE_PHYSC_LTSSM_STATE_MASK</a>&#160;&#160;&#160;0x000001F8</td></tr>
<tr class="memdesc:ga83dbe369846939579a0dd3d74476bcb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">LTSSM State Mask.  <a href="group__axipcie.html#ga83dbe369846939579a0dd3d74476bcb7">More...</a><br/></td></tr>
<tr class="separator:ga83dbe369846939579a0dd3d74476bcb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d873d3497027ad74b8d0240a28ab11d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga1d873d3497027ad74b8d0240a28ab11d">XAXIPCIE_PHYSC_LANE_REV_MASK</a>&#160;&#160;&#160;0x00000600</td></tr>
<tr class="memdesc:ga1d873d3497027ad74b8d0240a28ab11d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane Reversal Mask.  <a href="group__axipcie.html#ga1d873d3497027ad74b8d0240a28ab11d">More...</a><br/></td></tr>
<tr class="separator:ga1d873d3497027ad74b8d0240a28ab11d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b1c63c3222b1c3585b7b7ba73a46db8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga1b1c63c3222b1c3585b7b7ba73a46db8">XAXIPCIE_PHYSC_LINK_UP_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga1b1c63c3222b1c3585b7b7ba73a46db8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Up Status Mask.  <a href="group__axipcie.html#ga1b1c63c3222b1c3585b7b7ba73a46db8">More...</a><br/></td></tr>
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<tr class="memitem:ga238bcf6752996345861f9e958ee5bddc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga238bcf6752996345861f9e958ee5bddc">XAXIPCIE_PHYSC_DLW_MASK</a>&#160;&#160;&#160;0x00030000</td></tr>
<tr class="memdesc:ga238bcf6752996345861f9e958ee5bddc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width to change Mask.  <a href="group__axipcie.html#ga238bcf6752996345861f9e958ee5bddc">More...</a><br/></td></tr>
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<tr class="memitem:ga04fd250e831f12d2274e81fc11f8544a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga04fd250e831f12d2274e81fc11f8544a">XAXIPCIE_PHYSC_DLWS_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:ga04fd250e831f12d2274e81fc11f8544a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width Speed to change Mask.  <a href="group__axipcie.html#ga04fd250e831f12d2274e81fc11f8544a">More...</a><br/></td></tr>
<tr class="separator:ga04fd250e831f12d2274e81fc11f8544a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf6ed374b48c1d8d127a3cc0fa1dd082"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaaf6ed374b48c1d8d127a3cc0fa1dd082">XAXIPCIE_PHYSC_DLA_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:gaaf6ed374b48c1d8d127a3cc0fa1dd082"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Change change to reliability or Autonomus Mask.  <a href="group__axipcie.html#gaaf6ed374b48c1d8d127a3cc0fa1dd082">More...</a><br/></td></tr>
<tr class="separator:gaaf6ed374b48c1d8d127a3cc0fa1dd082"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3422457e569985908990b125ded1b5f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaf3422457e569985908990b125ded1b5f">XAXIPCIE_PHYSC_DLC_MASK</a>&#160;&#160;&#160;0x00300000</td></tr>
<tr class="memdesc:gaf3422457e569985908990b125ded1b5f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link change Mask.  <a href="group__axipcie.html#gaf3422457e569985908990b125ded1b5f">More...</a><br/></td></tr>
<tr class="separator:gaf3422457e569985908990b125ded1b5f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaef8ab25bd7ab6a989ddc832c2c50c2e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaef8ab25bd7ab6a989ddc832c2c50c2e4">XAXIPCIE_PHYSC_LINK_WIDTH_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gaef8ab25bd7ab6a989ddc832c2c50c2e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Status Shift.  <a href="group__axipcie.html#gaef8ab25bd7ab6a989ddc832c2c50c2e4">More...</a><br/></td></tr>
<tr class="separator:gaef8ab25bd7ab6a989ddc832c2c50c2e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41728830bc4094a6044ea629c4699201"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga41728830bc4094a6044ea629c4699201">XAXIPCIE_PHYSC_LTSSM_STATE_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga41728830bc4094a6044ea629c4699201"><td class="mdescLeft">&#160;</td><td class="mdescRight">LTSSM State Shift.  <a href="group__axipcie.html#ga41728830bc4094a6044ea629c4699201">More...</a><br/></td></tr>
<tr class="separator:ga41728830bc4094a6044ea629c4699201"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad478317d1ca0eae5e32d87e51bbb0a92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gad478317d1ca0eae5e32d87e51bbb0a92">XAXIPCIE_PHYSC_LANE_REV_SHIFT</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:gad478317d1ca0eae5e32d87e51bbb0a92"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane Reversal Shift.  <a href="group__axipcie.html#gad478317d1ca0eae5e32d87e51bbb0a92">More...</a><br/></td></tr>
<tr class="separator:gad478317d1ca0eae5e32d87e51bbb0a92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6b51f3442219824eb75fc8ff3cfe1660"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga6b51f3442219824eb75fc8ff3cfe1660">XAXIPCIE_PHYSC_LINK_UP_SHIFT</a>&#160;&#160;&#160;11</td></tr>
<tr class="memdesc:ga6b51f3442219824eb75fc8ff3cfe1660"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Up Status Shift.  <a href="group__axipcie.html#ga6b51f3442219824eb75fc8ff3cfe1660">More...</a><br/></td></tr>
<tr class="separator:ga6b51f3442219824eb75fc8ff3cfe1660"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e9344be85c4daabbe33825ec565e348"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga7e9344be85c4daabbe33825ec565e348">XAXIPCIE_PHYSC_DLW_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga7e9344be85c4daabbe33825ec565e348"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width to change Shift.  <a href="group__axipcie.html#ga7e9344be85c4daabbe33825ec565e348">More...</a><br/></td></tr>
<tr class="separator:ga7e9344be85c4daabbe33825ec565e348"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab4aba0340f18918d3aa073dfe631724c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gab4aba0340f18918d3aa073dfe631724c">XAXIPCIE_PHYSC_DLWS_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:gab4aba0340f18918d3aa073dfe631724c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width Speed to change Shift.  <a href="group__axipcie.html#gab4aba0340f18918d3aa073dfe631724c">More...</a><br/></td></tr>
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<tr class="memitem:ga39556f83d4e88ec7783db2826ce5303d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga39556f83d4e88ec7783db2826ce5303d">XAXIPCIE_PHYSC_DLA_SHIFT</a>&#160;&#160;&#160;19</td></tr>
<tr class="memdesc:ga39556f83d4e88ec7783db2826ce5303d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link change to reliability or Autonomus Shift.  <a href="group__axipcie.html#ga39556f83d4e88ec7783db2826ce5303d">More...</a><br/></td></tr>
<tr class="separator:ga39556f83d4e88ec7783db2826ce5303d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaabf018637b6aa1ca5b7ca4657ed2583a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaabf018637b6aa1ca5b7ca4657ed2583a">XAXIPCIE_PHYSC_DLC_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:gaabf018637b6aa1ca5b7ca4657ed2583a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link change Shift.  <a href="group__axipcie.html#gaabf018637b6aa1ca5b7ca4657ed2583a">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Root Port Status/Control Register bitmaps and masks</div></td></tr>
<tr class="memitem:ga727eba08077bad1923e3ff44e5522110"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga727eba08077bad1923e3ff44e5522110">XAXIPCIE_RPSC_MASK</a>&#160;&#160;&#160;0x0FFF0001</td></tr>
<tr class="memdesc:ga727eba08077bad1923e3ff44e5522110"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Register mask.  <a href="group__axipcie.html#ga727eba08077bad1923e3ff44e5522110">More...</a><br/></td></tr>
<tr class="separator:ga727eba08077bad1923e3ff44e5522110"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7239a578a5e3bbf80fac05bab9a841aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga7239a578a5e3bbf80fac05bab9a841aa">XAXIPCIE_RPSC_BRIDGE_ENABLE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga7239a578a5e3bbf80fac05bab9a841aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Enable Mask.  <a href="group__axipcie.html#ga7239a578a5e3bbf80fac05bab9a841aa">More...</a><br/></td></tr>
<tr class="separator:ga7239a578a5e3bbf80fac05bab9a841aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga306dded24643ad2589e7773a278198c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga306dded24643ad2589e7773a278198c2">XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:ga306dded24643ad2589e7773a278198c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Not Empty.  <a href="group__axipcie.html#ga306dded24643ad2589e7773a278198c2">More...</a><br/></td></tr>
<tr class="separator:ga306dded24643ad2589e7773a278198c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad476109c1b88e734cd0c487551ecd38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaad476109c1b88e734cd0c487551ecd38">XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:gaad476109c1b88e734cd0c487551ecd38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Overflow.  <a href="group__axipcie.html#gaad476109c1b88e734cd0c487551ecd38">More...</a><br/></td></tr>
<tr class="separator:gaad476109c1b88e734cd0c487551ecd38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad174b729ea9da546195a3e35b5306296"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gad174b729ea9da546195a3e35b5306296">XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:gad174b729ea9da546195a3e35b5306296"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Not Empty.  <a href="group__axipcie.html#gad174b729ea9da546195a3e35b5306296">More...</a><br/></td></tr>
<tr class="separator:gad174b729ea9da546195a3e35b5306296"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7e2cf8f647b545ca89191d281d28500"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gae7e2cf8f647b545ca89191d281d28500">XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:gae7e2cf8f647b545ca89191d281d28500"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Overflow.  <a href="group__axipcie.html#gae7e2cf8f647b545ca89191d281d28500">More...</a><br/></td></tr>
<tr class="separator:gae7e2cf8f647b545ca89191d281d28500"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae47e36bef3304c2ed171d5c4263b356"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaae47e36bef3304c2ed171d5c4263b356">XAXIPCIE_RPSC_COMP_TIMEOUT_MASK</a>&#160;&#160;&#160;0x0FF00000</td></tr>
<tr class="memdesc:gaae47e36bef3304c2ed171d5c4263b356"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Completion Timeout.  <a href="group__axipcie.html#gaae47e36bef3304c2ed171d5c4263b356">More...</a><br/></td></tr>
<tr class="separator:gaae47e36bef3304c2ed171d5c4263b356"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae31c1b6a918ba904627c85e1b1e90cd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gae31c1b6a918ba904627c85e1b1e90cd7">XAXIPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gae31c1b6a918ba904627c85e1b1e90cd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Empty Shift.  <a href="group__axipcie.html#gae31c1b6a918ba904627c85e1b1e90cd7">More...</a><br/></td></tr>
<tr class="separator:gae31c1b6a918ba904627c85e1b1e90cd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c13191564e035b1f82bd03a2618ae68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga4c13191564e035b1f82bd03a2618ae68">XAXIPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT</a>&#160;&#160;&#160;17</td></tr>
<tr class="memdesc:ga4c13191564e035b1f82bd03a2618ae68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Overflow Shift.  <a href="group__axipcie.html#ga4c13191564e035b1f82bd03a2618ae68">More...</a><br/></td></tr>
<tr class="separator:ga4c13191564e035b1f82bd03a2618ae68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac928e2b08d55a229e1bcb3064c420152"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gac928e2b08d55a229e1bcb3064c420152">XAXIPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:gac928e2b08d55a229e1bcb3064c420152"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Empty Shift.  <a href="group__axipcie.html#gac928e2b08d55a229e1bcb3064c420152">More...</a><br/></td></tr>
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<tr class="memitem:ga487c2d600b1745aeda32d7987c08ba79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga487c2d600b1745aeda32d7987c08ba79">XAXIPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT</a>&#160;&#160;&#160;19</td></tr>
<tr class="memdesc:ga487c2d600b1745aeda32d7987c08ba79"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Overflow Shift.  <a href="group__axipcie.html#ga487c2d600b1745aeda32d7987c08ba79">More...</a><br/></td></tr>
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<tr class="memitem:ga5bd566eee0347d55e43ce6c803fd9ea6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga5bd566eee0347d55e43ce6c803fd9ea6">XAXIPCIE_RPSC_COMP_TIMEOUT_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:ga5bd566eee0347d55e43ce6c803fd9ea6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Completion Timeout Shift.  <a href="group__axipcie.html#ga5bd566eee0347d55e43ce6c803fd9ea6">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Root Port MSI Base Register bitmaps and masks</div></td></tr>
<tr class="memitem:ga6b8ab2e2dd878a06c3fec3bef2612f88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga6b8ab2e2dd878a06c3fec3bef2612f88">XAXIPCIE_RPMSIB_UPPER_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga6b8ab2e2dd878a06c3fec3bef2612f88"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper 32 bits of 64 bit MSI Base Address.  <a href="group__axipcie.html#ga6b8ab2e2dd878a06c3fec3bef2612f88">More...</a><br/></td></tr>
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<tr class="memitem:gaf58383b79342a1ef51e2c00674f7d6dd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf58383b79342a1ef51e2c00674f7d6dd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIPCIE_RPMSIB_UPPER_SHIFT</b>&#160;&#160;&#160;32	   /* Shift of Upper 32 bits */</td></tr>
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<tr class="memitem:gac25094bce1e85b534dc154222a7d83a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gac25094bce1e85b534dc154222a7d83a3">XAXIPCIE_RPMSIB_LOWER_MASK</a>&#160;&#160;&#160;0xFFFFF000</td></tr>
<tr class="memdesc:gac25094bce1e85b534dc154222a7d83a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lower 32 bits of 64 bit MSI Base Address.  <a href="group__axipcie.html#gac25094bce1e85b534dc154222a7d83a3">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Root Port Error FIFO Read Register bitmaps and masks</div></td></tr>
<tr class="memitem:ga4e82350a3eb45f3f8a61351de81d39c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga4e82350a3eb45f3f8a61351de81d39c9">XAXIPCIE_RPEFR_REQ_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga4e82350a3eb45f3f8a61351de81d39c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester of Error Msg.  <a href="group__axipcie.html#ga4e82350a3eb45f3f8a61351de81d39c9">More...</a><br/></td></tr>
<tr class="separator:ga4e82350a3eb45f3f8a61351de81d39c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga76dd5672aa49d1675193c515ee99275e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga76dd5672aa49d1675193c515ee99275e">XAXIPCIE_RPEFR_ERR_TYPE_MASK</a>&#160;&#160;&#160;0x00030000</td></tr>
<tr class="memdesc:ga76dd5672aa49d1675193c515ee99275e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of Error.  <a href="group__axipcie.html#ga76dd5672aa49d1675193c515ee99275e">More...</a><br/></td></tr>
<tr class="separator:ga76dd5672aa49d1675193c515ee99275e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d7406f32c476e78d25f92fab2bbb30b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga0d7406f32c476e78d25f92fab2bbb30b">XAXIPCIE_RPEFR_ERR_VALID_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:ga0d7406f32c476e78d25f92fab2bbb30b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Read Succeeded Status.  <a href="group__axipcie.html#ga0d7406f32c476e78d25f92fab2bbb30b">More...</a><br/></td></tr>
<tr class="separator:ga0d7406f32c476e78d25f92fab2bbb30b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga285c4d376d023b3b9df54754606808df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga285c4d376d023b3b9df54754606808df">XAXIPCIE_RPEFR_ERR_TYPE_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga285c4d376d023b3b9df54754606808df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of Error Shift.  <a href="group__axipcie.html#ga285c4d376d023b3b9df54754606808df">More...</a><br/></td></tr>
<tr class="separator:ga285c4d376d023b3b9df54754606808df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb9ed69607f6da66cc0501f4f18bb732"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gacb9ed69607f6da66cc0501f4f18bb732">XAXIPCIE_RPEFR_ERR_VALID_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:gacb9ed69607f6da66cc0501f4f18bb732"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Read Succeeded Status Shift.  <a href="group__axipcie.html#gacb9ed69607f6da66cc0501f4f18bb732">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Root Port Interrupt FIFO Read 1 Register bitmaps and masks</div></td></tr>
<tr class="memitem:ga477d9111e2c1e6932b00b658cda9df01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga477d9111e2c1e6932b00b658cda9df01">XAXIPCIE_RPIFR1_REQ_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga477d9111e2c1e6932b00b658cda9df01"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester Id of Interrupt Message.  <a href="group__axipcie.html#ga477d9111e2c1e6932b00b658cda9df01">More...</a><br/></td></tr>
<tr class="separator:ga477d9111e2c1e6932b00b658cda9df01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2a9c673eaa9cdb18e3ac3788fcb834d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gad2a9c673eaa9cdb18e3ac3788fcb834d">XAXIPCIE_RPIFR1_MSI_ADDR_MASK</a>&#160;&#160;&#160;0x07FF0000</td></tr>
<tr class="memdesc:gad2a9c673eaa9cdb18e3ac3788fcb834d"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI Address.  <a href="group__axipcie.html#gad2a9c673eaa9cdb18e3ac3788fcb834d">More...</a><br/></td></tr>
<tr class="separator:gad2a9c673eaa9cdb18e3ac3788fcb834d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf545ca193095942641304d55ce7e416"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaaf545ca193095942641304d55ce7e416">XAXIPCIE_RPIFR1_INTR_LINE_MASK</a>&#160;&#160;&#160;0x18000000</td></tr>
<tr class="memdesc:gaaf545ca193095942641304d55ce7e416"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr Line Mask.  <a href="group__axipcie.html#gaaf545ca193095942641304d55ce7e416">More...</a><br/></td></tr>
<tr class="separator:gaaf545ca193095942641304d55ce7e416"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa573753049273f1ece6a4b24917d2b05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaa573753049273f1ece6a4b24917d2b05">XAXIPCIE_RPIFR1_INTR_ASSERT_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:gaa573753049273f1ece6a4b24917d2b05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether Interrupt INTx is asserted.  <a href="group__axipcie.html#gaa573753049273f1ece6a4b24917d2b05">More...</a><br/></td></tr>
<tr class="separator:gaa573753049273f1ece6a4b24917d2b05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d9b70e72dbf4e3db706b28f5f749e74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga9d9b70e72dbf4e3db706b28f5f749e74">XAXIPCIE_RPIFR1_MSIINTR_VALID_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga9d9b70e72dbf4e3db706b28f5f749e74"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether Interrupt is MSI or INTx.  <a href="group__axipcie.html#ga9d9b70e72dbf4e3db706b28f5f749e74">More...</a><br/></td></tr>
<tr class="separator:ga9d9b70e72dbf4e3db706b28f5f749e74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9a5f8ec646e50bdc31887a508f50fc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaf9a5f8ec646e50bdc31887a508f50fc5">XAXIPCIE_RPIFR1_INTR_VALID_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gaf9a5f8ec646e50bdc31887a508f50fc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Read Succeeded Status.  <a href="group__axipcie.html#gaf9a5f8ec646e50bdc31887a508f50fc5">More...</a><br/></td></tr>
<tr class="separator:gaf9a5f8ec646e50bdc31887a508f50fc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71868428e591d5f59fd40151da6d3aa5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga71868428e591d5f59fd40151da6d3aa5">XAXIPCIE_RPIFR1_MSI_ADDR_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga71868428e591d5f59fd40151da6d3aa5"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI Address Shift.  <a href="group__axipcie.html#ga71868428e591d5f59fd40151da6d3aa5">More...</a><br/></td></tr>
<tr class="separator:ga71868428e591d5f59fd40151da6d3aa5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0465365bbae94b36de39aceeb580cdd1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga0465365bbae94b36de39aceeb580cdd1">XAXIPCIE_RPIFR1_MSIINTR_VALID_SHIFT</a>&#160;&#160;&#160;30</td></tr>
<tr class="memdesc:ga0465365bbae94b36de39aceeb580cdd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI/INTx Interrupt Shift.  <a href="group__axipcie.html#ga0465365bbae94b36de39aceeb580cdd1">More...</a><br/></td></tr>
<tr class="separator:ga0465365bbae94b36de39aceeb580cdd1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabdd55507fa3a696908e3d31abe7ff1e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gabdd55507fa3a696908e3d31abe7ff1e6">XAXIPCIE_RPIFR1_INTR_VALID_SHIFT</a>&#160;&#160;&#160;31</td></tr>
<tr class="memdesc:gabdd55507fa3a696908e3d31abe7ff1e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Read Valid Shift.  <a href="group__axipcie.html#gabdd55507fa3a696908e3d31abe7ff1e6">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Root Port Interrupt FIFO Read 2 Register bitmaps and masks</div></td></tr>
<tr class="memitem:gaaf6ce74eb3d24d535f2c399330c27af9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gaaf6ce74eb3d24d535f2c399330c27af9">XAXIPCIE_RPIFR2_MSG_DATA_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gaaf6ce74eb3d24d535f2c399330c27af9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pay Load for MSI Message.  <a href="group__axipcie.html#gaaf6ce74eb3d24d535f2c399330c27af9">More...</a><br/></td></tr>
<tr class="separator:gaaf6ce74eb3d24d535f2c399330c27af9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">ECAM Address Register bitmaps and masks</div></td></tr>
<tr class="memitem:gabbe43193c1a1f1b12a1e8e2910ffb02e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gabbe43193c1a1f1b12a1e8e2910ffb02e">XAXIPCIE_ECAM_MASK</a>&#160;&#160;&#160;0x0FFFFFFF</td></tr>
<tr class="memdesc:gabbe43193c1a1f1b12a1e8e2910ffb02e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of all valid bits.  <a href="group__axipcie.html#gabbe43193c1a1f1b12a1e8e2910ffb02e">More...</a><br/></td></tr>
<tr class="separator:gabbe43193c1a1f1b12a1e8e2910ffb02e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39ab6deaee9fe1e2ab734e85dc0fad5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga39ab6deaee9fe1e2ab734e85dc0fad5c">XAXIPCIE_ECAM_BUS_MASK</a>&#160;&#160;&#160;0x0FF00000</td></tr>
<tr class="memdesc:ga39ab6deaee9fe1e2ab734e85dc0fad5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Number Mask.  <a href="group__axipcie.html#ga39ab6deaee9fe1e2ab734e85dc0fad5c">More...</a><br/></td></tr>
<tr class="separator:ga39ab6deaee9fe1e2ab734e85dc0fad5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c530b27ed7392d44e98855cbf1582fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga7c530b27ed7392d44e98855cbf1582fe">XAXIPCIE_ECAM_DEV_MASK</a>&#160;&#160;&#160;0x000F8000</td></tr>
<tr class="memdesc:ga7c530b27ed7392d44e98855cbf1582fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Number Mask.  <a href="group__axipcie.html#ga7c530b27ed7392d44e98855cbf1582fe">More...</a><br/></td></tr>
<tr class="separator:ga7c530b27ed7392d44e98855cbf1582fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b3e595d86874d13a20a84e998792ede"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga8b3e595d86874d13a20a84e998792ede">XAXIPCIE_ECAM_FUN_MASK</a>&#160;&#160;&#160;0x00007000</td></tr>
<tr class="memdesc:ga8b3e595d86874d13a20a84e998792ede"><td class="mdescLeft">&#160;</td><td class="mdescRight">Function Number Mask.  <a href="group__axipcie.html#ga8b3e595d86874d13a20a84e998792ede">More...</a><br/></td></tr>
<tr class="separator:ga8b3e595d86874d13a20a84e998792ede"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad62957cb703c4fdabd125b714ff3b113"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gad62957cb703c4fdabd125b714ff3b113">XAXIPCIE_ECAM_REG_MASK</a>&#160;&#160;&#160;0x00000FFC</td></tr>
<tr class="memdesc:gad62957cb703c4fdabd125b714ff3b113"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register Number Mask.  <a href="group__axipcie.html#gad62957cb703c4fdabd125b714ff3b113">More...</a><br/></td></tr>
<tr class="separator:gad62957cb703c4fdabd125b714ff3b113"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga188489525792d10a8892af78991ba828"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#ga188489525792d10a8892af78991ba828">XAXIPCIE_ECAM_BYT_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga188489525792d10a8892af78991ba828"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte Address Mask.  <a href="group__axipcie.html#ga188489525792d10a8892af78991ba828">More...</a><br/></td></tr>
<tr class="separator:ga188489525792d10a8892af78991ba828"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe54d275930774f3ef2fa61861cc1047"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gafe54d275930774f3ef2fa61861cc1047">XAXIPCIE_ECAM_BUS_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:gafe54d275930774f3ef2fa61861cc1047"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Number Shift Value.  <a href="group__axipcie.html#gafe54d275930774f3ef2fa61861cc1047">More...</a><br/></td></tr>
<tr class="separator:gafe54d275930774f3ef2fa61861cc1047"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8e00362272438c225cdf2bf5ee977e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axipcie.html#gad8e00362272438c225cdf2bf5ee977e7">XAXIPCIE_ECAM_DEV_SHIFT</a>&#160;&#160;&#160;15</td></tr>
<tr class="memdesc:gad8e00362272438c225cdf2bf5ee977e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Number Shift Value.  <a href="group__axipcie.html#gad8e00362272438c225cdf2bf5ee977e7">More...</a><br/></td></tr>
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